The present invention relates to a process for fabricating quantum-coupled electronic devices.
It is generally recognized that conventional VLSI integrated technical technology will be prevented from further scaling by the time MOS devices get down to a quarter micron channel length, and perhaps even at much larger geometries. Since much of the advance in integrated circuit capabilities has been based on the continued progress of scaling, this near-future barrier is of substantial concern.
Thus it is an object of the present invention to provide an integrated circuit technology wherein active devices can have active regions smaller than one quarter micron in dimension.
It is further object of the present invention to provide an integrated circuit technology wherein active devices can be fabricated which occupy a total area of less than 1/4 of a square micron average for each active device.
A further inherent limitation of conventional integrated circuit technology is speed. MOS devices have inherent limits on their speed due to the channel-length transit time. Intergrable bipolar devcies also have inherent speed limitations, due to the base width transit time, and are also likely to have high power dissipation.
Thus it is an object of the present invention to provide an active device having higher potential maximum speed than any MOS device.
It is a further object of the present invention to provide an active device which is potentially faster than any bipolar device.
It is a further object of the present invention to provide an active device which is potentially faster than any bipolar device, and which also has a very low power dissipation.
To achieve these and other objects, the present invention provides; a new genus of electronic devices, wherein at least two closely adjacent potential wells (e.g. islands of GaAs in an AlGaAs lattice) are made small enough that at least two components of momentum of carriers within the wells are discretely quantized. This means that, when the bias between the wells is adjusted to align energy levels of the two wells, tunneling will occur very rapidly, whereas when energy levels are not aligned, tunneling will be greatly reduced. This high-gain mechanism leads to useful electronic device functions.
However, these devices are exceedingly difficult to fabricate, due to their extremely small dimensions. In particular, for the embodiments which are capable of high temperature operation (i.e. room temperature or liquid nitrogen temperature operation), the geometries required must be even smaller yet. In addition, it is necessary to fabricate these extremely small geometry wells in such a manner that very good interface quality will be preserved at the boundaries of the wells.
Thus it is an object of the present invention to provide a process for fabrication of quantum-well devices, wherein quantum wells with maximum dimensions less than 500 Angstroms and with extremely good interface quality can be fabricated.
It is a further object of the present invention to provide a process for fabrication of quantum-well devices, wherein quantum wells with maximum dimensions less than 500 Angstroms and with extremely good interface quality can be fabricated, wherein contacts for coupling to the quantum wells are also fabricated.
It is a further object of the present invention to provide a process for fabrication of quantum-well devices, wherein quantum wells with maximum dimensions less than 150 Angstroms and with extremely good interface quality can be fabricated, wherein contacts for coupling to the quantum wells are also fabricated.
According to the present invention there is provided:
A process for fabricating quantum-well devices, comprising the steps of:
providing a substrate;
providing first and second epitaxial layers of a first semiconductor material on said substrate,
said first layer being doped to a concentration of at least 1E17 per cubic centimeter and being at least 200 nm thick, PA1 and said second layer comprising a dopant concentration no greater than 5E16 per cubic centimeter and a thickness less than 300 Angstroms;
anistropically etching trenches in a first pattern through said second layer but not entirely through said first layer;
epitaxially growing a second semiconductor material, which has a wider bandgap than said first semiconductor material and is approximately lattice-matched to said first semiconductor material, to substantially fill said trenches;
anisotropically etching trenches in a second pattern through both said first layer and said second layer into said substrate;
epitaxially growing said second semiconductor material, to substantially fill said second trenches; and
forming metallization to configure a desired circuit function;
wherein said first and second patterned trench etches jointly define a plurality of quantum wells within isolated portions of said second layer,
and wherein said second trench etch defines interconnections of said quantum wells within said first layer.